1. Field of the Invention
The present invention relates to an integrated semiconductor device with a wafer-level burn-in circuit and a function decision method of a wafer-level burn-in circuit for checking as to whether a wafer-level burn-in circuit for controlling wafer-level burn-in functions correctly or not.
2. Description of Related Art
Conventionally, wafer-level burn-in has been performed to remove defective integrated semiconductor devices including various types of memories such as DRAM and SRAM and/or various types of logic circuits by checking them by applying various stresses before factory shipment.
For example, Japanese patent application laid-open No. 9-17198/1997 discloses a technique relating to conventional wafer-level burn-in. The wafer-level burn-in checks as to whether an integrated semiconductor device operates properly by driving all the word lines simultaneously, and by comparing by an external tester the data read from memory cells in a memory core or the like with expected values prepared in advance. This will make it possible to remove the defective integrated semiconductor devices before shipment.
The conventional integrated semiconductor devices with such an arrangement undergo operation test that applies to the integrated semiconductor devices not only operation voltages higher or lower than those used in a bias accelerated test in normal burn-in, but also various stresses such as heating or cooling the integrated semiconductor devices. The operation test, however, has a problem in the reliability of the wafer-level burn-in because it cannot verify whether the wafer-level burn-in circuit functions correctly or not in performing and controlling the wafer-level burn-in.
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide an integrated semiconductor device with a wafer-level burn-in circuit and a function decision method of a wafer-level burn-in circuit capable of verifying whether the wafer-level burn-in circuit functions properly or not.
According to a first aspect of the present invention, there is provided an integrated semiconductor device with a wafer-level burn-in circuit comprising: a memory core including a plurality of memory cells; an access controller for controlling wafer-level burn-in operation by controlling input and output of control signals, an address signal and test data used by the wafer-level burn-in operation; and a test mode register for setting operation conditions of the wafer-level burn-in operation, wherein the integrated semiconductor device is set, when the test mode register is set in a test mode, in a DMA (direct memory access) mode that enables the address signal, the test data and prescribed voltages to be directly input from and output to outside, and is forcedly supplied with the prescribed voltages required for the wafer-level burn-in operation, wherein the access controller, being set in a wafer-level burn-in mode, supplies the memory core with the address signal and test data in accordance with a wafer-level burn-in operation condition which is set in the test mode register, and performs the wafer-level burn-in operation, and wherein the integrated semiconductor device reads, when the access controller is released from the wafer-level burn-in mode, the test data in the memory core in the DMA mode, and outputs the test data to the outside.
Here, the integrated semiconductor device with wafer-level burn-in circuit may further comprise an expected value comparator for reading the test data in the memory core after the wafer-level burn-in operation is completed and the access controller is released from the wafer-level burn-in mode, for comparing the test data read from the memory core with preset expected values, and for outputting a compared result, wherein the integrated semiconductor device may output the compared result obtained by the expected value comparator.
The access controller may perform the wafer-level burn-in operation by supplying the memory core with one of the address signal for selecting all word lines in the core memory simultaneously, the address signal for selecting only even number word lines simultaneously, and the address signal for selecting only odd number word lines simultaneously.
According to a second aspect of the present invention, there is provided a function decision method of a wafer-level burn-in circuit comprising the steps of: setting in a test mode a test mode register in which a wafer-level burn-in operation condition is set; setting an integrated semiconductor device with the wafer-level burn-in circuit in a DMA (direct memory access) mode that enables an address signal, test data and prescribed voltages to be directly input from and output to outside; forcedly applying the prescribed voltages required for the wafer-level burn-in operation to the integrated semiconductor device; performing the wafer-level burn-in operation, when an access controller in the wafer-level burn-in circuit is set in a wafer-level burn-in mode and supplies a memory core with the address signal and test data in accordance with the wafer-level burn-in operation condition set in the test mode register; releasing the access controller from the wafer-level burn-in mode after completing the wafer-level burn-in operation; reading the test data in the memory core in the DMA mode; and outputting the test data read from the memory core to the outside to be compared with expected values.
Here, the function decision method of the wafer-level burn-in circuit may further comprise the steps of: reading the test data from the memory core after releasing the access controller; comparing the test data read from the memory core with preset expected values; and outputting a compared result as a function decision result of the wafer-level burn-in circuit.